The C# float parser strikes again, I see…
And that theme is beautiful. What a masterpiece. I cried several times while listening to it. Could spend all day picking it apart and analyzing all its elements, but, suffice it to say, it does a fantastic job capturing the essence of Logic World.
Congratulations, Jimmy and Felipe, for making it this far. I’m sure you still have a long way to go to fulfill your aspirations, but this is an incredible milestone.
Actually just thought of another name - “isolator”. Not sure which one I like better, but buffer and isolator are my top two suggestions.
Name ideas for the diode (largely based on anthropomorphisms like the Oracle and Singer):
A diode can also be described as a “buffer” - I like the way that sounds, but it has a second definition in software (data buffers) which might cause some confusion for people approaching this game with CS/software backgrounds as opposed to electrical and computer engineering. But I’ll use it for the rest of this comment to make it stick in your head :)
If I understand correctly, there’s still a drawback to the linker layer - the performance benefits break down when there’s a long chain of relays and/or buffers, because propagating updates each tick across all of them is going to be linear with respect to the length of the chain. While this may not be a problem for small circuits, I can imagine some builds where TPS might suffer (for example, using relays to implement instant carry on 64 or even 32 bit adders).
This is also a problem that I’m also working on solving for FlipFlop, to see if I can lower the complexity of those updates. I do like the 2-layer approach, something like that could be used to speed up graph updates for things like sockets, which connect and disconnect larger circuits when boards are moved, and I’m planning on having a socket-like component in FlipFlop. However because Logic World has dynamically-connecting components like relays (and also now asymmetric connections thanks to buffers), the optimization problem is definitely not as easy.
As for exclusive pegs, they would allow for more compact builds compared to buffers. Especially because the input peg for buffers isn’t exclusive, meaning you need 1 buffer per input wire, whereas with exclusive pegs, all of the wires can connect to the same peg. However I do like the idea of moving that functionality into an explicitly separate component.
In fact, it’d be interesting to make exclusive pegs into a standalone component, with a single exclusive input and an instant propagation, (or perhaps 1 tick if it needs balance). Actually, I think I just described an OR - like the AND gate component that already exists, the inputs are isolated from each other and from the output, unlike a “wire-OR”.
I would also try compressing the files instead of using varints. Something like LZ4 would easily beat the space saved from varints, and it would be much less complex to add another layer of I/O versus a custom function for reading and writing integers that has to be applied everywhere. Time overhead is definitely larger, but based on the results from this benchmark it could easily be around 5ms per megabyte.
Anxiously awaiting your apt affirmation of … Well dang, I suck at writing alliterations at 6am.
Can’t wait to hear more about your improvements to relays!